Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
Semiconductor devices are often fabricated by depositing a series of layers on a substrate. Some or all of the layers include various patterned structures. The relative position of structures both within particular layers and between layers is critical to the performance of completed electronic devices. Overlay refers to the relative position of overlying or interlaced structures on the same or different layers of a wafer. Overlay error refers to deviations from the nominal (i.e., desired) relative position of overlying or interlaced structures. The greater the overlay error, the more the structures are misaligned. If the overlay error is too great, the performance of the manufactured electronic device may be compromised.
Overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. Traditionally, optical metrology techniques have been employed to perform overlay measurements. In some examples, image based overlay (IBO) metrology techniques are employed. IBO measurements involve imaging specialized targets based on reflected light. The target structures may take many forms, such as a box in box structure or bar-in-bar structure. In one example, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available. The overlay is measured by processing each image to estimate the distance between target features printed on different layers from the measured images.
Unfortunately, these specialized target structures often do not conform to the design rules of the particular semiconductor manufacturing process being employed to generate the electronic device. This leads to errors in estimation of overlay errors associated with actual device structures that are manufactured in accordance with the applicable design rules. For example, IMO metrology often requires the pattern to have thick lines with critical dimensions far exceeding design rule critical dimensions to be successfully resolved with an optical microscope.
In some other examples, light scattered or diffracted from overlay targets is employed to estimate overlay. Scatterometry based overlay metrology techniques, commonly referred to as scatterometry overlay (SCOL) or diffraction based overlay (DBO), are based primarily on differential measurements of optical signals corresponding to diffraction from two different targets, each with programmed overlay offsets. The unknown overlay error is extracted based on these differential measurements.
Most existing scatterometry based methods characterize overlay error based on a metric sensitive to asymmetry of the structure. For example, existing angle-resolved scatterometry overlay (SCOL) characterizes overlay based on the measured asymmetry between the +1 and −1 diffracted orders. However, relying solely on asymmetry as the indicator of overlay error is problematic because process induced variations, including both symmetric and asymmetric variations, significantly affect the overlay measurement. For example, asymmetric process variations such as sidewall angle asymmetry, line profile asymmetry or beam illumination asymmetry couple into the overlay-generated asymmetry in the measurement signal. This results in an inaccurate measurement of overlay error. In other examples, symmetric process variations such as film thickness variations couple into the overlay-generated asymmetry in the measurement signal.
Traditionally, the lack of robustness to process variations in SCOL and DBO (i.e., changes in non-overlay parameters that affect measured asymmetry) is addressed by selecting a specific illumination wavelength that is less sensitive to process variations and optimizing the target design to reduce sensitivity to process variations. Unfortunately, both of these approaches are limited in their effectivity. For example, the selection of a specific illumination wavelength may result in small overlay measurement errors, but only within a small range of the full process window. This makes the measurement unreliable and inconsistent, requiring frequent reevaluation of illumination wavelength. Target design optimization is very time consuming and requires accurate models of the structures, material dispersions, and the optical system. It is also very challenging to verify the accuracy of the models because the mask and targets are typically not available at the time of recipe development. In addition, target optimization may reduce measurement sensitivity to process variations, but does not fully address robustness to the full window of process variations.
FIGS. 1A-1C illustrate pupil images of one measured diffraction order associated with a SCOL measurement performed at three different illumination wavelengths. FIG. 1A depicts an image 10 of a measured diffraction order at an illumination wavelength of 523 nanometers. FIG. 1B depicts an image 11 of a measured diffraction order at an illumination wavelength of 579 nanometers. FIG. 1C depicts an image 12 of a measured diffraction order at an illumination wavelength of 668 nanometers.
As illustrated in FIG. 1B, the measured image 11 is distorted by an arc through the middle of the image due to resonance at that wavelength. The total intensity of the measured diffraction order is affected by the resonance arc as well as the resulting overlay estimate. Images 10 and 12 do not exhibit such a distortion and the resulting overlay estimates associated with these illumination wavelengths are more accurate.
FIG. 2 depicts a plot 13 of inaccuracy of overlay measurement by a SCOL system over a range of wavelengths. Plotline 14 depicts three different wavelength sub-ranges where overlay inaccuracy spikes to unacceptable levels. Points 15-17 correspond with the illumination wavelengths illustrated in FIGS. 1A-1C, respectively. FIG. 2 is commonly referred to as an inaccuracy landscape. Such a plot is useful for analyzing overlay inaccuracies and robustness to process variations.
A current approach to recipe development for a particular overlay measurement application is to avoid the wavelength sub-regions where inaccuracy spikes. However, the presence of symmetric and asymmetric process variations causes shifts in the inaccuracy landscape which complicates the selection of a suitable illumination wavelength.
FIG. 3 depicts a plot 20 of several inaccuracy landscapes, each associated with a different value of line profile asymmetry. Plotline 21 depicts inaccuracy with no line profile asymmetry. Plotline 22 depicts inaccuracy with line profile asymmetry of 2 nanometers. Plotline 23 depicts inaccuracy with line profile asymmetry of 4 nanometers. Plotline 24 depicts inaccuracy with line profile asymmetry of 8 nanometers. As illustrated in FIG. 3, as structural asymmetry increases, for example, due to printing errors, the amplitude of the induced inaccuracy of the overlay measurement increases. In this example, the increase in inaccuracy is linearly proportional to the amplitude of the line profile asymmetry.
FIG. 4 depicts a plot 30 of several inaccuracy landscapes, each associated with a different value of height variation of the overlay structure, a symmetrical process variation. Plotline 31 depicts inaccuracy with no height variation. Plotline 32 depicts inaccuracy with height variation of +6 nanometers. Plotline 33 depicts inaccuracy with height variation of −6 nanometers. As illustrated in FIG. 4, as the symmetric process variation changes, the inaccuracy landscape shifts in wavelength.
FIGS. 3 and 4 illustrate that overlay inaccuracy depends on symmetric and asymmetric variations. Overlay errors are amplified by asymmetric process variations and shift in wavelength by symmetric process variations. Peaks of overlay inaccuracy are not fixed at specific wavelengths in the presence of symmetric process variations. As a result, the selection of a suitable illumination wavelength based on a particular inaccuracy landscape may prove inadequate in the presence of asymmetric and symmetric process variations. One may attempt to mitigate this risk by selecting the illumination wavelength in light of a number of inaccuracy landscapes that encompass a range of symmetric and asymmetric process variations, but in some examples, the variations may be so large that there is no illumination wavelength that will result in a sufficiently accurate overlay measurement. As a result, in some cases, it is impossible to generate an overlay measurement recipe based on the selection of illumination wavelength.
Additional description of inaccuracy landscapes is presented by Bringholz, Barak, et al. in “Accuracy in optical overlay metrology,” Proc. of SPIE, Vol 9778, 9778H-1-19, published Mar. 24, 2016, the subject matter of which is incorporated herein by reference in its entirety.
Conventional SCOL and DBO techniques require four different targets (e.g., a metrology target having four different cells) to measure overlay in two directions (i.e., two cells associated with each different direction). This increases move-acquire-measure (MAM) times and target area on the wafer.
In addition, the overlay accuracy of conventional SCOL and DBO techniques is significantly affected by optical system variations and aberrations. This makes it difficult to achieve accurate overlay measurements and sufficiently accurate tool matching.
Future overlay metrology applications present challenges for metrology due to increasingly small resolution requirements and the increasingly high value of wafer area. Thus, methods and systems for improved overlay measurements are desired.